The present invention relates to the field of digital computer systems, and more specifically, to instruction processing with a processor having multiple execution units.
Processors such as superscalar processors, allow parallel execution of several instructions during a single processor cycle due to the availability of a plurality of parallel execution units. Generally, this mechanism increases the processor's performance. However, two consecutive instructions may be dependent on each other. For example, a following instruction may require the result of the preceding instruction. Thus, a scheduling or dispatching of the following instruction has to wait for the preceding instruction to finish. Independent of this, an issuing of instructions to different execution units may be performed without reflecting these special dependencies resulting in performance issues due to the communication delay overhead of results between execution units. Thus, there is a need for improving the scheduling of the dependent instructions.